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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75512(A)
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75512(A) is a 4-bit single-chip microcomputer which employs 75X series architecture, and its performance is comparable to that of an 8-bit microcomputer. In addition to its high-speed processing capabilities, the PD75512(A) is also capable of processing data in units of 1, 4, or in 8-bits. With its internally provided A/D converter and serial interface, the PD75512(A) provides the highest performance in its class. Detailed functions are described in the following user`s manual. Be sure to read it for designing.
PD75516 User`s Maual: IEM-5049
FEATURES
* Higher reliability than PD75512 * Adequate I/O lines: 64 (can be provided with pull-up/pull-down resistors: 47) * Built-in 8-bit serial interface: 2-ch NEC standard serial bus interface (SBI) internally provided * Built-in 8-bit A/D converter: 8-ch * Variable instruction execution time function which is convenient for high-speed operation and power saving * 0.95 s/1.95 s/15.3 s (at 4.19 MHz operation), * 122 s (at 32.768 kHz operation) * Program memory (ROM) size: 12,160 x 8 bits * Data memory (RAM) size: 512 x 4 bits * High-performance timer function: 4-ch * 8-bit timer/event counter * Watch timer * 8-bit basic interval timer * Timer/pulse generator: Capable of outputting 14-bit PWM * Clock operation for reduced power consumption possible (5 A TYP. at 3 V operation) * PROM version (PD75P516) available
APPLICATIONS
Switable for automotive and transportation equipments, etc.
The information in this document is subject to change without notice.
Document No. IC-2815A (O. D. No. IC-8265A) Date Published January 1994 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1991
PD75512(A)
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 20mm) Remarks: xxx is ROM code number. Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Difference between PD75512(A) and PD75512 Quality Grade Special
PD75512GF(A)-xxx-3B9
Product Item Quality Grade
PD75512(A)
PD75512
Special
Standard
Absolute Maximum Ratings Electrical Specifications DC Characteristics
Differ in high-level and low-level output current
Differ in low-level output voltage
A/D Converter Characteristics
Differ in ambient temperature range and absolute accuracy
2
PD75512(A)
PD75512(A) FUNCTIONS
Item Internal Memory Size ROM RAM 12160 x 8 bits 512 x 4 bits (4 bits x 8 or 8 bits x 4) x 4 banks * 0.95 s/1.91 s/15.3 s (Main system clock: at 4.19 MHz) * 122 s (Subsystem clock: at 32.768 kHz) 64 lines 16 lines (also serve as INT, SIO, PPO, analog input; can be pulled up by software: 7 lines) 28 lines * Can be pulled up by software: 16 lines * Can be pulled down by mask option: 4 lines 20 lines (10 V withstand voltage; pins that can be pulled up by mask option: 20) 8-bit resolution x 8 channels (successive approxmation type) * Operation voltage: VDD = 3.5 to 6.0 V Function
5
Genearl-Purpose Register Instruction Cycle
Total CMOS Inputs Input/ Output Ports
CMOS Input/Outputs
N-ch Open-Drain Input/Outputs A/D Converter
Timer/Counter
4 channels

* * * *
Timer/event counter Basic interval timer Timer/pulse generator (capable of outputting 14-bit PWM) Watch timer
Serial Interface Vector Interrupt Test Input
2 channels
* NEC standard serial bus interface (SBI)/3-line SIO: 1 channel * Normal clock synchronized serial interface (3-line SIO): 1 channel
External: 3, Internal: 4 External: 1, Internal: 1 * Bit data set/reset/test/boolean operation instruction * 4-bit data transfer/operation/increment/decrement /compare instructions * 8-bit data transfer/operation/increment/decrement /compare instructions * Ceramic/crystal oscillator for main system clock: 4.19 MHz * Crystal oscillator for subsystem clock: 32.768 kHz VDD = 2.7 V to 6.0 V 80-pin plastic QFP (14 x 20mm)
Instruction Set
System Clock Generator Operation Voltage Package
3
PD75512(A)
CONTENTS
1.
PIN CONFIGURATION .....................................................................................................................
6
2.
INTERNAL BLOCK DIAGRAM .........................................................................................................
7
3.
PIN FUNCTIONS ..............................................................................................................................
3.1 3.2 3.3 3.4 3.5 PORT PINS ............................................................................................................................................. NON-PORT PINS ................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ............................................................................................................ RECOMMENDED CONDITIONS FOR UNUSED PINS .......................................................................... MASK OPTION SELECTION .................................................................................................................
8
8 10 11 14 15
4.
MEMORY CONFIGURATION ..........................................................................................................
16
5.
PERIPHERAL HARDWARE FUNCTIONS ........................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 PORT ...................................................................................................................................................... CLOCK GENERATOR CIRCUIT ............................................................................................................. CLOCK OUTPUT CIRCUIT ..................................................................................................................... BASIC INTERVAL TIMER ...................................................................................................................... WATCH TIMER ...................................................................................................................................... TIMER/EVENT COUNTER ..................................................................................................................... TIMER/PULSE GENERATOR ................................................................................................................. SERIAL INTERFACE ............................................................................................................................... A/D CONVERTER ................................................................................................................................... BIT SEQUENTIAL BUFFER ...................................................................................................................
19
19 20 21 22 23 23 25 26 30 31
6.
INTERRUPT FUNCTIONS ................................................................................................................
31
7.
STANDBY FUNCTIONS ...................................................................................................................
33
8.
RESET FUNCTIONS .........................................................................................................................
34
9.
INSTRUCTION SET ..........................................................................................................................
36
10. ELECTRICAL SPECIFICATIONS .......................................................................................................
44
11. PACKAGE DRAWINGS ....................................................................................................................
57
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................
4
58
PD75512(A)
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PD755XX(A) SERIES PRODUCTS ............. APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 59
60
APPENDIX C. RELATED DOCUMENTS ................................................................................................
61
5
PD75512(A)
1. PIN CONFIGURATION
AN4/P150
AN5/P151
AN6/P152
AN7/P153
P120
P121
P122
P130
P131
P132
AN0 AVREF V DD * VDD P113 P112 P111 P110 P103 P102 P101 P100 P93 P92 P91 P90 SI1/P83 SO1/P82 SCK1/P81 PPO/P80 KR7/P73 KR6/P72 KR5/P71 KR4/P70
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
P123
P133
AN3
AVSS
AN1
AN2
P140 P141 P142 P143 RESET X2 X1 IC XT2 XT1 V SS P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30
PD75512GF(A) - xxx-3B9
21 22 23
41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
KR1/P61
P51
P42
P41
P33
P32
KR3/P63
KR2/P62
KR0/P60
P53
P52
P50
IC: Internally Connected (Connect directly to VSS)
*: Power must be supplied to both VDD pins.
6
P43
P40
P31
VSS
2.
BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 BANK BUZ/P23 WATCH TIMER PROGRAM COUNTER (14) ALU CY SP (8)
PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 DECODE AND CONTROL PORT 8 RAM DATA MEMORY 512 x 4 BITS PORT10 PORT 9
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
P00-P03
INTERNAL BLOCK DIAGRAM
P10-P13 P20-P23 P30-P33 P40-P43* P50-P53* P60-P63 P70-P73 P80-P83 P90-P93 P100-P103 P110-P113 P120-P123* P130-P133* P140-P143* P150-P153
INTW ROM PPO/P80 TIMER/PULSE GENERATOR INTTPG SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SERIAL INTERFACE0 INTCSI SI1/P83 SO1/P82 SCK1/P81 SERIAL INTERFACE1 PROGRAM MEMORY 12160 x 8 BITS
GENERAL REG.
PORT11 PORT12 PORT13
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 8 -KR7/P73 INTERRUPT CONTROL CLOCK OUTPUT CONTROL PCL/P22 BIT SEQ. BUFFER (16) AN0-AN3
f X /2 N CLOCK DIVIDER CLOCK GENERATOR SUB XT1 MAIN X2 STAND BY CONTROL
PORT14 CPU CLOCK RESET VDD VSS PORT15
PD75512(A)
XT2 X1
AN4/P150-AN7/P15
AVREF AVSS
A/D CONVERTER
*: PORTs 4, 5, and 12 to 14 are 10 V middle voltage, N-ch open-drain input/output ports.
7
PD75512(A)
3.
3.1
PIN FUNCTIONS
PORT PINS (1/2)
Input/ Output Circuit Type* B F -A x Input F -B M -C With noise elimination function 4-bit input port (PORT1). Built-in pull-up resistors can be specified by software in 4-bit units. x Input B -C
Pin Name
Input/ Output
Shared Pin
Function
8-bit I/O
When Reset
P00 P01 Input P02 P03 P10 P11 Input P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 Input/ output Input/ output
INT4 SCK0 SO0/SB0 SI0/SB1 INT0 INT1 INT2 TI0 PTO0 -- PCL BUZ -- -- -- --
4-bit input port (PORT0). For P01 to P03, built-in pull-up resistors can be specified in 3-bit units by software.
4-bit input/output port (PORT2). Built-in pull-up resistors can be specified by software in 4-bit units.
x
Input
E-B
Programmable 4-bit input/output port (PORT3). Input/output can be specified in bit units. Built-in pull-up resistors can be specified by software in 4-bit unit.
x
Input
E-C
P40 to P43
Input/ output
--
N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. O N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. Programmable 4-bit input/ output port (PORT6). Input/output can be specified in bit units. Built-in pull-up resistors can be specified by software in 4-bit units.
High level (when pull-up resistor is provided) or high impedance
M
P50 to P53
Input/ output
--
High level (when pull-up resistor is provided) or high impedance
M
P60 P61 P62 P63 Input/ output
KR0 KR1 KR2 KR3
O
Input
F -C
*: The number enclosed with a circle indicates Schmitt trigger input.
8
PD75512(A)
3.1 PORT PINS (2/2)
Input/ Output Circuit Type*
Pin Name
Input/ Output
Shared Pin
Function
8-bit I/O
When Reset
P70 P71 P72 P73 P80 P81 Input P82 P83 Input/ output
KR4 KR5 KR6 KR7 PPO SCK1 4-bit input port (PORT8). SO1 SI1 Low level (when pulldown resistor is provided) or high impedance Input x x Input E B E F 4-bit input/output port (PORT7). Built-in pull-up resistor can be specified in 4-bit units by software.
O
Input
F -A
P90 to P93
Input/ output
--
4-bit input/output port (PORT9). Built-in pull-up resistors can be specified in bit units by mask option.
x
V
P100 to P103 P110 to P113
Input/ output Input/ output
--
4-bit input/output port (PORT10).
E
--
4-bit input/output port (PORT11).
Input
E
P120 to P123
Input/ output
--
N-ch open-drain 4-bit input/output port (PORT12). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. N-ch open-drain 4-bit input/output port (PORT13). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. N-ch open-drain 4-bit input/output port (PORT14). A pull-up resistor can be provided in bit units (mask option). 10V withstanding voltage in the open-drain mode. 4-bit input port (PORT15).
x
High level (when pull-up resistor is provided) or high impedance
M
P130 to P133
Input/ output
--
x
High level (when pull-up resistor is provided) or high impedance
M
P140 to P143
Input/ output
--
x
High level (when pull-up resistor is provided) or high impedance
M
P150 to P153
Input
AN4 to AN7
x
Input
Y-A
*: The number enclosed with a circle indicates Schmitt trigger input.
9
PD75512(A)
3.2 NON-PORT PINS
Input/ Output Circuit Type* B -C E-B E-B E-B F -A F -B M -C B
Pin Name
Input/ Output
Shared Pin
Function
When Reset
TI0 PTO0 PCL BUZ SCK0 SO0/SB0 SI0/SB1 INT4 INT0
Input Output Output Output Input/ output Input/ output Input/ output Input
P13 P20 P22 P23 P01 P02 P03 P00 P10
The external event pulse input for the timer/event counter. Timer/event counter output Clock output Fixed frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial bus input/output Serial data input Serial bus input/output Edge detection vector interrupt input (both rising edge and falling edge detection) Edge detection vector interrupt input (detection edge selectable) Edge detection testable input (rising edge detection) Synchronized with clock
-- Input Input Input Input Input Input --
Input INT1 INT2 KR0-KR3 KR4-KR7 SCK1 SO1 SI1 AN0-AN3 Input AN4-AN7 AVREF AVSS Input -- P150-P153 -- -- Input Input Input Input/ output Output Input P11 P12 P60-P63 P70-P73 P81 P82 P83 --
-- Asynchronous Asynchronous -- Input Input Input Input Input --
B -C B -C F -C F -A F E B Y
Parallel falling edge detection testable input Parallel falling edge detection testable input Serial clock input/output Serial data output Serial data input A/D converter analog input A/C converter reference voltage input A/D converter reference ground Pins for connecting the crystal ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. Pins for connecting the crystal oscillator to the subsystem clock generator. When the external clock is used, inputs the external clock to pin XT1. In this case, pin XT2 must be left open. System reset input Timer/pulse generator pulse output Internally Connected. Connect directly to VSS. Positive power supply GND
Y-A -- -- Z --
X1, X2
Input
--
--
--
XT1 XT2 RESET PPO IC VDD VSS
Input -- -- Input Output -- -- -- -- P80 -- -- --
--
--
-- Input -- -- --
B E -- -- --
*: The number enclosed with a circle indicates Schmidt trigger input. 10
PD75512(A)
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the PD75512(A).
TYPE A
VDD
TYPE D
VDD data P-ch P-ch OUT
IN N-ch output disable
N-ch
Input buffer of CMOS standard
Push-pull output that can be set in a output high-impedance state (both P-ch and N-ch are off)
TYPE B
TYPE E
data Type D IN output disable
IN/OUT
Type A
Schmitt trigger input with hysteresis characteristics
This input/output circuit consists of D-type push-pull outputs and Type A input buffers.
TYPE B-C
TYPE E-B
VDD P.U.R. P.U.R. enable P-ch
VDD P.U.R. P-ch P.U.R. enable
data Type D output disable
IN/OUT
IN
Type A
P.U.R. : Pull-Up Resistor Schmitt trigger input with hysteresis characteristics P.U.R. : Pull-Up Resistor
Fig. 3-1 Pin Input/Output Circuits (1/3)
11
PD75512(A)
Type E-C
VDD
Type F-B
VDD P.U.R. P.U.R. P.U.R. enable VDD P-ch data output disable output disable (N-ch) IN/OUT N-ch P-ch
P.U.R. enable data Type D output disable
P-ch
output disable (P-ch)
IN/OUT
Type A
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Type F
Type F-C
VDD
data Type D output disable
P.U.R. IN/OUT P.U.R. enable data
Type B
P-ch
IN/OUT Type D
output disable
Type B
This input/output circuit consists of D-type push-pull outputs and Type B Schmitt trigger inputs.
P.U.R. : Pull-Up Resistor
Type F-A
VDD P.U.R. P.U.R. enable P-ch
Type M
VDD P.U.R. (Mask Option)
IN/OUT
data Type D output disable
IN/OUT
data output disable
N-ch
(can withstand up to +10 V)
Type B
P.U.R. : Pull-Up Resistor
Middle-voltage input buffer (can withstand up to +10 V) P.U.R. : Pull-Up Resistor
Fig. 3-1 Pin Input/Output Circuits (2/3)
12
PD75512(A)
Type M-C
VDD P.U.R. P.U.R. enable P-ch IN/OUT data output disable N-ch IN
Type Y-A
IN instruction
V DD P-ch N-ch V DD Sampling C AVSS + -
AVSS Reference voltage (from a voltage tap of series resistor string) input enable
P.U.R. : Pull-Up Resistor
Type V
Type Z
data Type D output disable
AV REF IN/OUT
Type A
Reference voltage P.D.R (Mask Option)
P.D.R. : Pull-Down Resistor
AVSS
Type Y
V DD IN V DD Sampling C AVSS P-ch N-ch + -
AVSS Reference voltage (from a voltage tap of series resistor string) Input enable
Fig. 3-1 Pin Input/Output Circuits (3/3)
13
PD75512(A)
5 3.4 RECOMMENDED CONDITIONS FOR UNUSED PINS
Table 3-1 Recommended Conditions for Unused Pins
Pin P00/INT4 P01/ SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0-P12/INT2 Connect to VSS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ Input state: Connect to VSS or VDD P30-P33 Output state: Open P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80/PPO P81/ SCK1 Connect to VSS or VDD P82/SO1 P83/SI1 P90-P93 P100-P103 P110-P113 P120-P123 P130-P133 P140-P143 P150/AN4-P153/AN7 Connect to VSS AN0-AN3 XT1 XT2 AVREF Connect to VSS AVSS IC Connect directly to VSS Connect to VSS or VDD Open Input state: Connect to VSS or VDD Output state: Open Connect to VSS or VDD Recommended Conditions Connect to VSS
14
PD75512(A)
3.5 MASK OPTION SELECTION
The following mask options are provided with the pins. (1) Pull-up/pull-down resistor selection
Table 3-2 Pull-up/Pull-down Resistor Selection
Pins P40-P43 P50-P53 P120-P123 P130-P133 P140-P143 P90-P93 (1) With pull-down resistor (Can be specified in bit units) (2) Without pull-down resistor (Can be specified in bit units) (1) With pull-up resistor (Can be specified in bit units) Mask Option (2) Without pull-up resistor (Can be specified in bit units)
(2)
Feedback resistor selection for the subsystem clock oscillation
5
Table 3-3 Feedback Resistor Selection
Pins XT1, XT2 Mask Option (1) With feedback resistor (When the subsystem clock is used) (2) Without feedback resistor (When the subsystem clock is not used)
Note:
The operation is not affected if the feedback resistor is selected when the subsystem clock is not used. However, the supply current IDD is increased.
15
PD75512(A)
5
4.
MEMORY CONFIGURATION * Program memory (ROM) ... 12160 x 8 bits (0000H-2F7FH)
* 0000H, 0001H : * 0002H-000DH : Vector table to which address from which program is started is written after reset Vector table to which address from which program is started is written after
interrupt * 0020H-007FH : Table area referenced by GETI instruction
* Data memory
* Data area .... 512 x 4 bits (000H-1FFH) * Peripheral hardware area .... 128 x 4 bits (F80H-FFFH)
16
PD75512(A)
Address 7 0000H 6 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE RBE INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE RBE INTCSIO0 start address (upper 6 bits) INTCSIO0 start address (lower 8 bits) 000AH MBE RBE INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTTPG start address (upper 6 bits) INTTPG start address (lower 8 bits) BRCB !caddr instruction branch address CALLF !faddr instruction entry address BR !addr instruction branch address CALL !addr instruction subroutine entry address 0
MBE RBE
BR $addr instruction relational branch address (-15 to -1, +2 to +16)
0020H GETI instruction reference table 007FH 0080H Branch destination address and subroutine entry address for GETI instruction
007FH 0800H
0FFFH 1000H BRCB !caddr instruction branch address 1FFFH 2000H BRCB !caddr instruction branch address 2F7FH
Remarks:
In addition to the above, branching to an address, for which only the lower 8 bits of the PC are modified, is possible by the BR PCDE and BR PCXA instructions.
Fig. 4-1 Program Memory Map
17
PD75512(A)
Data memory General 000H purpose register 01FH area 008H Stack area (32 x 4)
Memory bank
256x 4
0
Data area Static RAM (512 x 4) 0FFH 100H
256x 4
1
1FFH
Unmapped
F80H
Peripheral hardware area
128x 4
15
FFFH
Fig. 4-2 Data Memory Map
18
PD75512(A)
5.
5.1 * * *
PERIPHERAL HARDWARE FUNCTIONS
PORT CMOS input (PORTS 0, 1, 8, 15) CMOS input/output (PORTS 2, 3, 6, 7, 9, 10, 11) N-ch open-drain input/output (PORTS 4, 5, 12, 13, 14) : 16 : 28 : 20 : 64
5
I/O ports are classified into following kinds:
Total
Table 5-1 Port Functions
Port (Pin Name) PORT0 4-bit input PORT1 Can be specified for I/O in 4-bit units 4-bit I/O Can be specified for I/O in 1/4-bit units. 4-bit I/O (N-ch open-drain, can sustain with 10V) Function Operation/Feature Remarks Also serves as the INT4, SCK0 , SO0/SB0, and SI0/SB1 pins Also serves as INT0 to 2, and TIO pins Also serves as PTO0, PCL and BUZ pins. -- Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option
Can be read or tested regardless of the operation mode of the shared pin.
PORT2 PORT3 PORT4
Can be specifiedfor I/O in 4-bit units
PORT5
Ports 4 and 5 can be paired to I/O data in 8-bit units
PORT6 4-bit I/O PORT7
Can be specified for I/O in 1/4-bit units Can be specified I/O in 4-bit units 4-bit input
Ports 6 and 7 can be paired to I/O data in 8-bit units
Also serves as KR0-3.
Also serves as KR4-7.
PORT8
Can be read or tested regardless of the operation mode of the shared pin.
Also serves as PPO, SCK1, SO1, and SI1 pins. Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option.
PORT9
4-bit I/O
Can be specified for I/O in 4-bit units.
PORT10 4-bit I/O PORT11 PORT12 PORT13 PORT14 PORT15 4-bit I/O (N-ch open-drain, can sustain with 10V) 4-bit Input Whether or not the internal pull-up resistor is provided can be specified for each bit by mask option. Can be specified for I/O in 4-bit units. --
Can be specified for I/O in 4-bit units.
Can be read or tested regardless of the operation mode of the shared pins
Also serves as AN4-7 pins.
19
PD75512(A)
6.2 CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. * 0.95 s, 1.91 s, 15.3 s (main system clock: 4.19 MHz) * 122 s (subsystem clock: 32.768 kHz)
* Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * Clock output circuit * A/D converter * INT0 noise rejecter circuit
V DD
XT1 XT2 X1 X2 Main system f X clock oscillator Subsystem clock oscillator f XT Watch timer Timer/pulse generator
V DD
1/8 to 1/4096 Frequency divider 1/2 1/16
SCC3
Internal bus
Selector
WM.3 SCC
Selector
Oscillator disable signal
Frequency divider 1/4 * CPU * Clock output circuit * INT0 noise rejecter circuit
SCC0 PCC PCC0 PCC1 4 PCC2 HALT* STOP* PCC3 R
HALT F/F S Q
PCC2, PCC3 clear signal
STOP F/F Q S R
Wait release signal from BT RESET signal Standby release signal from interrupt control circuit
*: instruction execution. Remarks 1: fX = Main system clock frequency 2: fXT = Subsystem clock frequency 3: = CPU clock 4: PCC: Processor clock control register 5: SCC: System clock control register 6: One clock cycle (tCY) of is one machine cycle of an instruction. For tCY, refer to AC characteristics in 10. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
20
PD75512(A)
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. * Clock output (PCL): , 524 kHz, 262 kHz, 65.5 kHz (operating at 4.19 MHz)
From the clock generator fX/23 Selector fX/24 fX/26 PCL/P22 Output buffer
PORT2.2 CLOM3 CLOM2 CLOM1 CLOM0 CLOM
P22 output latch
Bit 2 of PMGB
Port 2 input/ output mode specification bit
4 Internal bus
Fig. 5-2 Clock Output Circuit Configuration
Remarks:
A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken.
21
PD75512(A)
5.4 BASIC INTERVAL TIMER
The basic interval timer has these functions: * Interval timer operation which generates a reference time interrupt * Watchdog timer application which detects a program runaway * Selects the wait time for releasing the standby mode and counts the wait time * Reads out the count value
From the clock generator Clear fX/25 Clear
fX/27 MPX fX/29 BT Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
fX/212
Vector interrupt request IRQBT signal
3
Wait release signal for standby release BTM0 BTM
BTM3
BTM2
BTM1
SET1*
4 Internal bus
8
*: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
22
PD75512(A)
5.5 WATCH TIMER
The PD75512(A) has a built-in 1-ch watch timer. The watch timer has these functions. * Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. * 0.5 second interval can be generated either from the main system clock or subsystem clock. * Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. * Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. * The frequency divider circuit can be cleared so that zero second watch start is possible.
fW (256 Hz: 3.91 ms) 27 fX From the 128 (32.768 kHz) clock generator f XT (32.768 kHz) fW 2 14 (2 Hz 0.5 sec) Selector INTW (IRQW set signal)
Selector
fW (32.768 kHz)
Frequency divider
f W (2.048 16 kHz)
Clear Output buffer P23/BUZ
WM WM7 0 0 0 0 WM2 WM1 WM0 Bit test instruction Internal bus
PORT2.3
P23 output latch
Bit 2 of PMGB
Port 2 input/output mode
8
Remarks: ( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
Fig. 5-4 Watch Timer Block Diagram
5.6 TIMER/EVENT COUNTER The timer/event counter has these functions:
The PD75512(A) has a built-in 1-ch timer/event counter. * Programmable interval timer operation
* Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. * Event counter operation * Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). * Supplies serial shift clock to the serial interface circuit. * Count condition read out function
23
24
Internal bus 8 SET1* TM0 8 8 TMOD0 TOE0 TO enable flag Coincidence PORT2.0 P20 output latch Bit 2 of PGMB
Port 2 input/ output mode
TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
Modulo register (8)
PORT1.3
8 Comparator (8)
To serial interface
TOUT F/F Reset Output buffer
P20/PTO0
Input buffer P13/TI0 From the clock generator MPX
8 T0 Count register (8) CP Clear Timer operation start signal
(
INTT0 IRQT0 set signal
)
RESET IRQT0 clear signal *:Instruction execution
Fig. 5-5 Timer/Event Counter Block Diagram
PD75512(A)
PD75512(A)
5.7 TIMER/PULSE GENERATOR
The PD75512(A) contains a timer/pulse generator, that can be used as the timer or the pulse generator. Timer/ pulse generator has the following functions. (a) Function, when used in the timer mode * 8-bit interval timer operation (IRQTPG generation), for which the clock source can be changed in 5 steps. * Square waveform output to the PPO pin (b) Function, when used in the PWM pulse generation mode * 14-bit accuracy PWM pulse output to PPO pin (can be used as a D/A converter for electronics tuning). * Fixed time interval interrupt generation (2 /fX = 7.81ms: fX = 4.19 MHz) When no pulse output is required, the PPO pin can be used as 1-bit output port. Note: When setting the STOP mode, if the timer pulse generator is in operating mode, erroneous operation may occur. Therefore, the timer/pulse generator must be set in no-operation state by the mode register, before setting the STOP mode.
15
Internal bus
8 MODL Modulo register L (8) TPGM3 (Set to 1 )
8 MODH Modulo register H (8)
Modulo latch H (8) 8 Coincidence Comparator (8) Frequency divider fx 1/2 Prescaler select latch (5) Clear T F/F Set
INTTPG (IRQTPG set signal)
Output buffer Selector PPO
CP
8 Count register (8) Clear
TPGM4 TPGM5 TPGM7
TPGM1
Fig. 5-6 Timer/Pulse Generator Block Diagram (Timer Mode)
25
PD75512(A)
Internal bus
MODH Modulo register H (8)
MODL Modulo register L (8)
TPGM3
MODH(8) Modulo latch (14)
MODL7-2 (6) Output buffer
TPGM1 fx 1/2
PWM pulse generator
Selector
PPO
Frequency divider
INTTPG IRQTPG set signal (2 = 7.8 ms: f x at 4.19MHz) fx
15
TPGM5
TPGM7
Fig. 5-7 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)
5.8 SERIAL INTERFACE
The PD75512(A) is provided with two serial interface channels. Table 5-2 indicates differences between channel 0 and channel 1.
Table 5-2 Differences Between Channel 0 and Channel 1
Serial Transfer Mode, Funciton Clock Selection 3-Line Serial I/O Transfer Method Transfer Completion Flag 2-Line Serial I/O Usable Serial Bus Interface (SBI) Unprovided
4 3
Channel 0 fX/2 , fX/2 , TOUT F/F, external clock MSB first/LSB first selectable Serial transfer completion interrupt request flag (IRQCSI0)
4 3
Channel 1 fX/2 , fX/2 external clock MSB first Serial transfer completion flag (EOT)
(1)
Serial interface function (Channel 0) The PD75512(A) is equipped with the following four modes: * Operation stop mode * Three-line serial I/O mode * Two-line serial I/O mode * SBI mode (serial bus interface mode)
26
Internal bus
8/4
Bit test 8 8
8
Slave address register (SVA)
Bit manipulation (8) RELT CMDT
SET CLR
Bit test SBIC
CSIM0
Address comparator P03/SI/SB1
Selector
Coincidence signal (8)
SO0 latch
Shift register (SIO0)
(8)
D
Q
P02/SO/SB0
Selector
Busy/ acknowledge output circuit
Bus release/ command/ acknowledge detector circuit P01/SCK0
RELD CMDD ACKD
ACKT ACKE BSYE
Serial clock counter P01 output latch
INTCSI0 control circuit
(
MPX
INTCSI0 IRQCSI0 set signal
)
Serial clock control circuit
fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK0
PD75512(A)
Fig. 5-8 Serial Interface (Channel 0) Block Diagram
27
PD75512(A)
(2) Serial interface (Channel 1) configuration
PD75512(A) serial interface (channel 1) has following two modes.
* Operation stop mode * 3-line serial I/O mode
28
Internal bus Bit manipulation SIO1 write signal (serial start signal) 7 Shift register 1 (8) SIO1 bit 7 Serial operation mode (8) register 1 (8) Bit manipulation 0 CSIM1
8 bit 0 P83/SI1
8
P82/SO1
Clear Serial clock counter (3) Overflow Set
Serial transfer completion flag (EOT)
Clear P81/SCK1 R Q S MPX fx /24 fx /23
PD75512(A)
Fig. 5-9 Serial Interface (Channel 1) Block Diagram
29
PD75512(A)
5.9 A/D CONVERTER
The PD75512(A) is provided with an 8-bit resolution analog-to-digital (A/D) converter with eight channels of analog inputs (AN0-AN7). This A/D converter is of a successive approximation type.
Internal bus
8
0
ADM6 ADM5 ADM4
SOC
EOC
ADM1
0
ADM 8
AN0 AN1 AN2
Multiplexer
Control circuit
Sample hold circuit + - Comparator SA register (8)
AN3 AN4 AN5 AN6 AN7
8
Tap decoder
AVREF R/2 R R R R/2
AVSS
Fig. 5-10 Block Diagram of A/D Converter
30
PD75512(A)
5.10 BIT SEQUENTIAL BUFFER ..... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units.
Address bit 3 Symbol
FC3H 2 BSB3 1 0 3
FC2H 2 BSB2 1 0 3
FC1H 2 BSB1 1 0 3
FC0H 2 BSB0 1 0
L register
L=F
L=C L=B INCS L
L=8 L=7 DECS L
L=4 L=3
L=0
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-11 Bit Sequential Buffer Format
6.
INTERRUPT FUNCTIONS
The PD75512(A) has 7 different interrupt sources and multiplexed interrupt with priority order. In addition to that, the PD75512 is also provided with two types of test sources, of which INT2 has two types
of edge detection testable inputs. The interrupt control circuit of the PD75512(A) has these functions: * Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). * The interrupt start address can be arbitrarily set. * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). * Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
31
Selector
32
Internal bus 2 IM2 2 IM1 2 IM0 Interrupt enable flag (IExxx) (IME) 4 IPS 2 IST INT BT INT4 /P00 INT0 /P10 INT1 /P11 Both edge detection circuit Edge Noise detection elimination circuit circuit Edge detection circuit INTCSI0 INTT0 IRQBT IRQ4 IRQ0 IRQ1 IRQCSI0 IRQT0 Priority control circuit Vector table address generator VRQn Decoder INTTPG INTW INT2 /P12 Rising edge detection circuit Falling edge detection circuit IRQTPG IRQW IRQ2 Standby release signal KR0/P60 KR7/P73
PD75512(A)
IM2
Fig. 6-1 Interrupt Control Block Diagram
PD75512(A)
7. STANDBY FUNCTIONS
In order to fully exploit the PD75512(A) low power dissipation, CPU operation can be stopped by setting the unit to the standby mode, thus, further reducing power dissipation. The PD75512(A) features two standby modes, a STOP mode and a HALT mode.
Table 7-1 Status in Standby Mode
Mode Item Instruction for Setting System Clock at the Time of Setting Clock Oscillator Basic Interval Timer Serial Interface (Channel 0) Serial Interface (Channel 1) Operation Status Timer/Event Counter Clock Timer A/D Converter Timer/Pulse Generator Timer/Pulse Generator CPU Release Signal STOP Mode STOP instrtuction Can be set only when operating on the main system clock Only the main system clock can stop its operation. Does not operate Can operate only when the external SCK0 input is selected as the serial clock Can operate only when the external SCK1 input is selected as the serial clock Can only operate when the TI0 pin input is selected as system clock Operates when fXT is selected as the count clock Does not operate Does not operate HALT Mode HALT instruction Can be set when operating either on the main system clock or the subsystem clock Only the CPU clock stops its operation. (oscillation continues) Operates (Sets IRQBT with the reference time interval) Operates when the timer system clock is operating or external SCK0 is selected Operates only when the main system clock is operating Operates only when the main system clock is operating Can operate Operates only when the main system clock is operating Operates only when the main system clock is operating
INT1, INT2, and INT4 can operate, but INT0 cannot operate
Does not operate An interrupt request signal from a piece of hardware, whose operation is enabled by the interrupt enable flag, or the RESET signal input
33
PD75512(A)
8. RESET FUNCTIONS
When the RESET signal is input, the PD75512(A) is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing.
Wait (31.3ms/4.19MHz) RESET input
Operation mode or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware Program Counter (PC) RESET Input in Standby Mode The contents of the lower 6 bits of address 0000H of the program memory are set to PC13-8, and the contents of address 0001H are set to PC7-0. Retained 0 0 The contents of bit 6 of address 0000H of the program memory are set to RBE and those of bit 7 are set to MBE. Undefined Retained * Retained 0, 0 Undefined 0 0 FFH 0 0, 0 Retained 0 0 RESET Input during Operation
Same as left
PSW
Carry Flag (CY) Skip Flag (SK0-2) Interrupt Status Flag (IST0, 1) Bank Enable Flag (MBE, RBE)
Undefined 0 0
Same as left
Stack Pointer (SP) Data Memory (RAM) General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS, RBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Modulo Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Timer/Pulse Generator Watch Timer Modulo Register Mode Register Mode Register (WM)
Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 Retained 0 0
*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.
34
PD75512(A)
Table 8-1 Status of Each Hardware after Reset (2/2)
Hardware Serial Interface (Channel 0) Shift Register (SIO0) Operation Mode Register (CSIM0) SBI Control Register (SBIC) Slave Address Register (SVA) P01/SCK0 Output Latch A/D Converter Mode Regiseter (ADM), EOC SA Register Clock Generator, Clock Output Circuit Processor Clock Control Register (PCC) System Clock Control Register (SCC) Clock Output Mode Register (CLOM) Serial Interface (Channel 1) Shift Register (SIO1) Operation Mode Register 1 (CSIM1) Serial Transfer End Flag (EOT) Interrupt Function Interrupt Request Flag (IRQxxx) Interrupt Enable Flag (IExxx) Interrupt Master Enable Flag (IME) INT0, INT1, INT2 Mode Registers (IM0, 1, 2) Digital Port Output Buffer Output Latch Input/Output Mode Register (PMGA, B, C) Pull-Up Resistor Specification Register (POGA) Bit Sequential Buffer (BSB0-3) RESET Input in Standby Mode Retained 0 0 Retained 1 04H (EOC = 1) 7FH 0 0 0 Retained 0 0 Reset (0) 0 0 0, 0, 0 Off Clear (0) 0 0 RESET Input during Operation Undefined 0 0 Undefined 1 04H (EOC = 1) 7FH 0 0 0 Undefined 0 0 Reset (0) 0 0 0, 0, 0 Off Clear (0) 0 0
Retained
Undefined
35
PD75512(A)
9. INSTRUCTION SET
(1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data.
Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr PORTn IExxx RBn MBn Description X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 2F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (where bit0 = 0) or label PORT0 to PORT15 IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG RB0-RB3 MB0, MB1, MB15
*: Only even addresses can be described in mem when processing 8-bit data.
36
PD75512(A)
(2) A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE Legend of operation field : A register; 4-bit accumulator : B register; 4-bit accumulator : C register; 4-bit accumulator : D register; 4-bit accumulator : E register; 4-bit accumulator : H register; 4-bit accumulator : L register; 4-bit accumulator : X register; 4-bit accumulator : Register pair (XA); 8-bit accumulator : Register pair (BC); 8-bit accumulator : Register pair (DE); 8-bit accumulator : Register pair (HL); 8-bit accumulator : Expanded register pair (XA') : Expanded register pair (BC') : Expanded register pair (DE') : Expanded register pair (HL') : Program counter : Stack pointer : Carry flag; or bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag
PORTn : Port n (n = 0 to 15) IME IPS IExxx RBS MBS PCC . (xx) xxH : Interrupt mask enable flag : Interrupt priority selector register : Interrupt enable flag : Memory bank selector register : Memory bank selector register : Processor clock control register : Delimiter of address and bit : Contents addressed by xx : Hexadecimal data
37
PD75512(A)
(3) Symbols in addressing area field
*1 *2 *3 MB = MBE . MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-2F7FH addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH (PC13, 12 = 00B) or 1000H-1F7FH (PC13, 12 = 01B) or 2000H-2F7FH (PC13, 12 = 10B) faddr = 0000H-07FFH taddr = 0020H-007FH Program memory addressing Data memory addressing
*4 *5 *6 *7 *8
*9 *10
Remarks 1: 2: 3: 4: (4)
MB indicates memory bank that can be accessed. In *2, MB = 0 regardless of MBE and MBS. In *4 and *5, MB = 15 regardless of MBE and MBS. *6 to *10 indicate areas that can be addressed.
Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip
function skips. The value of S varies as follows: * When no instruction is skipped ************************************************************* S = 0 * When 1-byte or 2-byte instruction is skipped ************************************** S = 1 * When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ******* S = 2
Note : The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock , (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC).
38
PD75512(A)
Machine Bytes Cycles 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8+DE)ROM XA (PC13-8+XA)ROM *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B Addressing Area
Instructions
Mnemonics
Operand
Operation
Skip Conditions String effect A
Transfer MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A,mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
Table Reference
MOVT
XA, @PCDE XA, @PCXA
39
PD75512(A)
Machine Bytes Cycles 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 Addressing Area *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
Instructions Bit Transfer
Mnemonics MOV1
Operand
Operation CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A,CY A+(HL)+CY XA,CY XA+rp'+CY rp'1,CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A,CY A-(HL)-CY XA,CY XA-rp'-CY rp'1,CY rp'1-XA-CY AA AA
Skip Conditions
CY, fmem.bit CY, pmem.@L CY, @H+mem. bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
Arithme- ADDS tic Operation
A,#n4 XA,#n8 A,@HL XA,rp' rp'1,XA
ADDC
A,@HL XA,rp' rp'1,XA
SUBS
A,@HL XA,rp' rp'1,XA
*1
borrow borrow borrow
SUBC
A,@HL XA,rp' rp'1,XA
*1
AND
A,#n4 A,@HL XA,rp' rp'1,XA
n4 (HL)
*1
XA XA-rp'
OR
A,#n4 A,@HL XA,rp' rp'1,XA
XOR
A,#n4 A,@HL XA,rp' rp'1,XA
XA n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA
rp'1 rp'1 AA
*1
*1
40
PD75512(A)
Instructions
Mnemonics
Operand
Bytes
Machine Cycles 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1
Operation CY A0, A3 CY, An-1 An A A reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY
Addressing Area
Skip Conditions
Accumu- RORC lator Manipulation
A A reg rp1 @HL mem
1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
NOT INCS
Increment/ Decrement
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
DECS
reg rp'
Compari- SKE son
reg,#n4 @HL,#n4 A,@HL XA,@HL A,reg XA,rp'
Carry Flag
SET1 CLR1
CY CY CY CY
Manipu- SKT lation NOT1
CY = 1
41
PD75512(A)
Machine Bytes Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 -- Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1
Instructions
Mnemonics
Operand mem.bit fmem.bit pmem.@L @H+mem.bit
Operation (mem.bit) 1
(fmem.bit) 1
Skip Conditions
Memory/ SET1 Bit Manipulation CLR1
(pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1
(mem.bit) 0 (fmem.bit) 0
mem.bit fmem.bit pmem.@L @H+mem.bit
(pmem7-2 + L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0
Skip if (fmem.bit) = 1 and clear
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit Branch BR addr
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1 and clear
Skip if (H+mem3-0.bit) = 1 and clear
CY CY CY CY CY
(fmem.bit)
CY CY (pmem7-2+L3-2.bit(L1-0))
(H+mem3-0.bit) CY (fmem.bit) (H+mem3-0.bit) (fmem.bit) (H+mem3-0.bit)
CY CY (pmem7-2+L3-2.bit (L1-0))
CY CY CY CY CY CY
CY CY (pmem7-2+L3-2.bit (L1-0))
PC13-0 addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) PC13-0 addr PC13-0 addr PC13-0 PC13,12+caddr11-0 PC13-0 PC13-8+DE PC13-0 PC13-8+XA
!addr $addr BRCB BR !caddr PCDE PCXA
3 1 2 2 2
3 2 2 3 3
*6 *7 *8
42
PD75512(A)
Machine Bytes Cycles 3 3 Addressing Area *6
Instructions Subroutine/ Stack Control
Mnemonics CALL
Operand !addr
Operation (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13,12 PC13-0 addr, SP SP-4 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13,12 PC13-0 00, faddr, SP SP-4 MBE, RBE, PC13,12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4 MBE, RBE, PC13,12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally PC13,12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 (SP-1)(SP-2) rp, SP SP-2
(SP-1) MBS, (SP-2) RBS, SP SP-2
Skip Conditions
CALLF
!faddr
2
2
*9
RET
1
3
RETS
1
3+S
Undefined
RETI
1
3
PUSH POP Interrupt Control I/O DI EI
rp BS rp BS IExxx IExxx
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
rp (SP+1)(SP), SP SP+2
MBS (SP+1), RBS (SP), SP SP+2
IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn XA PORTn+1,PORTn PORTn A PORTn+1,PORTn XA
(n = 0-15) (n = 4, 6) (n = 2-7, 9-14) (n = 4, 6)
IN
*
1
A,PORTn XA,PORTn PORTn,A PORTn,XA
OUT * 1 CPU Control Special HALT STOP NOP SEL
Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n
(n = 0-3)
RBn MBn
2 2 1
GETI * 2 taddr
MBS n (n = 0, 1, 15) . Where TBR instruction, PC13-0 (taddr)4-0+(taddr+1) ......................................................... . Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13,12 PC13-0 (taddr)5-0+(taddr+1) SP SP-4 ......................................................... . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1)
*10 .............................
............................. Depends on referenced instruction
*1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. *2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of GETI instruction.
43
PD75512(A)
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Other than ports 4, 5, 12-14 Ports 4, 5, 12-14 w/pull-up resistor Open drain Output Voltage High-Level Output Current VO IOH* 1 pin All pins Low-Level Output Current Total of ports 0, 2, 3, 4 Total of ports 5-11 Total of ports 12-14 Operating Temperature Storage Temperature Topt Tstg IOL* 1 pin Peak rms Peak rms Peak rms Peak rms Peak rms Peak rms Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -10 -5 -30 -15 10 5 100 60 100 60 40 25 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
*: rms = Peak value x Duty
OPERATING SUPPLY VOLTAGE
Parameter A/D Converter Timer/Pulse Generator Other Circuits Supply voltage Ambient temperature Supply voltage Ambient temperatuare Supply voltage Ambient temperatuare Symbol VDD Ta VDD Ta VDD Ta Conditions MIN. 3.5 -40 4.5 -40 2.7 -40 MAX. 6.0 +85 6.0 +85 6.0 +85 Unit V C V C V C
CAPACITANCE (Ta = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/Output Capacitance Symbol CI CO CIO f = 1 MHz Pins other than thosemeasured are at 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
44
PD75512(A)
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Ceramic
Item Oscillation frequency(fX)*1
Conditions VDD = osccillation voltage range
MIN. 1.0
TYP.
MAX. 5.0 *3
Unit MHz
X1 C1
X2 C2
Oscillation stabiliza- After VDD came to MIN. value of tion time*2 oscillation voltage range
4
ms
Crystal
X1 C1 X2 C2
Oscillation frequency (fX)*1 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
1.0
4.19
5.0
*3
MHz ms ms
10 30
External Clock
X1 X2
X1 input frequency (fX)*1 X1 input high-, low-level widths (tXH, tXL)
1.0
5.0
*3
MHz
PD74HCU04
100
500
ns
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Crystal
Item Oscillation*1 frequency (fXT)
Conditions
MIN. 32
TYP. 32.768 1.0
MAX. 35 2 10
Unit kHz s s
XT1
XT2 R
Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
C3
C4
External Clock
XT1 Open XT2
XT1 input frequency (fXT)*1 XT1 input high-, low-level widths (tXTH, tXTL)
32
100
kHz
5
15
s
*1: Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. 5
45
PD75512(A)
5 Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit.
46
PD75512(A)
DC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 VIH3 Conditions Ports 2, 3, 9-11, P80, P82 Ports 0, 1, 6, 7, 15, P81, P83, RESET Ports 4, 5, 12-14 w/pull-up resistor Open-drain VIH4 Low-level Input Voltage VIL1 VIL2 VIL3 High-Level Output Voltage Low-Level Output Voltage VOL VOH X1, X2, XT1 Ports 2-5, 9-14, P80, P82 Ports 0, 1, 6, 7, 15, P81, P83, RESET X1, X2, XT1 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A Ports 3, 4, and 5 VDD = 4.5 to 6.0 V, IOL = 5 mA MIN. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 0.2 1.0 0.4 0.5 Open-drain Pull-up resistor 1 k Other than below X1, X2, XT1 VI = 9 V VI = 0 V Ports 4, 5, 12-14 (open-drain) Other than below X1, X2, XT1 VO = VDD VO = 9 V VO = 0 V Ports 0, 1, 2, 3, 6, 7 (except P00) VI = 0V Ports 4, 5, 12-14 VO = VDD-2.0 V VO = 2 V VDD = 5.0 V10% VDD = 3.0 V10% VDD = 5.0 V10% VDD = 3.0 V10% Port 9 15 30 15 10 20 70 40 40 Other than below Ports 4, 5, 12-14 (open-drain) 0.2VDD 3 20 20 -3 -20 3 20 -3 80 300 70 60 140 TYP. MAX. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V V V V
VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A SB0, 1 High-Level Input Leakage Current ILIH1 ILIH2 ILIH3 Low-Level Input Leakage Current High-Level Output Leakage Current ILIL1 ILIL2 ILOH1 ILOH2 ILOL VI = VDD
A A A A A A A A
k k k k k
Low-Level Output Leakage Current
Internal Pull-Up Resistor RU1
RU2
Internal Pull-Down Resistor
RD
47
PD75512(A)
Parameter Supply Current *1 Symbol IDD1 IDD2 IDD3 IDD4 IDD5 XT1 = 0 V STOP mode 4.19 crystal oscillator C1 = C2 = 22pF MHz*2 Conditions Ooperation mode HALT mode VDD = 5 V10%* 3 VDD = 3 V10%* 4 VDD = 5 V10% VDD = 3 V10% 32.768 kHz*5 crystal Operation oscillator mode HALT mode VDD = 3 V10% VDD = 3 V10% MIN. TYP. 3 0.55 600 200 40 5 0.5 0.3 Ta = 25C MAX. 9 1.5 1800 600 120 15 20 10 5 Unit mA mA
A A A A A A A
VDD = 5 V10%
VDD = 3 V10%
*1: Currents for the built-in pull-up resistor are not included. 2: Including when the subsystem clock is operated. 3: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 4: When operated in the low-speed mode with the PCC set to 0000. 5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation.
48
PD75512(A)
AC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V) (1) Basic Operation
Parameter CPU Clock Cycle Time*1 (Minimum Instruction Execution Time = 1 Machine Cycle) TI0 Input Frequency TI0 Input High-, Low-Level Widths Interrupt Input High-, Low-Level Widths Symbol tCY Conditions w/main system clock w/sub-system clock fTI tTIH, tTIL tINTH, tINTL VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INT0 INT1, 2, 4 KR0-7 RESET Low-Level Width tRSL VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 0 0.48 1.8 *2 10 10 10 122 TYP. MAX. 64 64 125 1 275 Unit
s s s
MHz kHz
s s s s s s
*1: The CPU clock () cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at the main system clock. 2: 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
Cycle time tCY [s]
70 64 60 6 5 Guaranteed operating range 4 3 tCY vs VDD (with main system clock)
2
1
0.5 0 1 2 3 4 5 6 Supply voltage VDD [V]
49
PD75512(A)
(2) Serial Transfer Operation (a) Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 tKH1 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 (tKCY1/2)-50 (tKCY1/2)-150 150 400 RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI Set-Up Time (vs. SCK ) tSIK1 SI Hold Time (vs. SCK ) tKSI1 SCK SO Output Delay Time tKSO1
*: RL and CL are load resistance and load capacitance of the SO output line.
(b)
Two-Line and Three-Line Serial I/O Modes (SCK: external clock input)
Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 tKH2 tKSI2 tKSO2 RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 400 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI Set-Up Time (vs. SCK ) tSIK2 SI Hold Time (vs. SCK ) SCK SO Output Delay Time
*: RL and CL are load resistance and load capacitance of the SO output line.
50
PD75512(A)
(c) SBI Mode (SCK: internal clock output (master))
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 tKCY3/2-50 tKCY3/2-150 150 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
(d)
SBI Mode (SCK: external clock input (slave))
Parameter Symbol tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width
*: RL and CL are load resistance and load capacitance of the SO output line.
51
PD75512(A)
(3) A/D Converter (Ta = -40 to +85C, VDD = 3.5 to 6.0 V, AVSS = VSS = 0 V)
Parameter Resolution Absolute Accuracy*1 Conversion Time*3 Sampling Time*4 Analog Input Voltage Analog Input Impedance AVREF Current tCONV tSAMP VIAN RAN AIREF
1 - LSB) 2
Symbol
Conditions 2.5 V AVREF VDD* 2
MIN. 8
TYP. 8
MAX. 8 2.0 168/fX 44/fX
Unit bit LSB
s s
V M mA
AVSS 1000 1.0
AVREF 2.0
*1: Absolute accuracy excluding quantization error (
2: Set ADM1 as follows, in respect to the reference voltage of the AD converter (AVREF).
2.5 V AV REF
0.6 V DD
0.65 V DD
V DD (3.5 to 6.0 V)
ADM1=0 ADM1=1
ADM1 can be set to either 0 or 1 when 0.6VDD AVREF 0.65VDD 3: Time since execution of conversion start instruction until EOC = 1 (40.1 s: fX = 4.19 MHz) 4: Time since execution of conversion start instruction until end of sampling (10.5 s: fX = 4.19 MHz)
52
PD75512(A)
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 VDD Test points 0.2 VDD
0.8 VDD 0.2 VDD
CLOCK TIMING
1/fX tXL tXH
X1 input
VDD -0.5V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD -0.5V 0.4 V
TI0 TIMING
1/fTI tTIL tTIH
TI0
53
PD75512(A)
SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
TWO-LINE SERIAL I/O MODE:
tKCY2 tKL2 tKH2
SCK
tKSO2
tSIK2
tKSI2
SB0,1
54
PD75512(A)
SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1 tKSO3,4
COMMAND SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
INTERRUPT INPUT TIMING
tINTL
tINTH
INT0, 1, 2, 4 KR0-7
RESET INPUT TIMING:
tRSL
RESET
55
PD75512(A)
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -40 to +85C)
Parameter Data Retention Supply Voltage Data Retention Supply Current*1 Release Signal Set Time Oscillation Stabilization Wait Time*2 Symbol VDDDR IDDDR tSREL tWAIT Released by RESET Released by interrupt VDDDR = 2.0 V 0 217/fX *3 Conditions MIN. 2.0 0.1 TYP. MAX. 6.0 10 Unit V
A s
ms ms
*1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT time ( ): fX = 4.19 MHz 2 20/fX (approx. 250 ms) 2 17/fX (approx. 31.3 ms) 2 15/fX (approx. 7.82 ms) 2 13/fX (approx. 1.95 ms)
DATA RETENTION TIMING (releasing STOP mode by RESET)
Internal reset operation HALT mode Operation mode
STOP mode Data retention mode
VDD VDDDR STOP instruction execution RESET tSREL
tWAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL
tWAIT
56
PD75512(A)
11. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40 detail of lead end
D
C
S
80 1
25 24
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
57
PD75512(A)
12. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD75512(A) be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, consult NEC.
Table 12-1 Soldering Conditions of Surface Mount Type
PD75512GF(A)-xxx-3B9: 80-pin plastic QFP (14 x 20 mm)
Soldering Method Infrared Reflow Soldering Conditions Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1 Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1 Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., time: 3 seconds max. (per side) Symbol for Recommended Condition IR30-00-1
VPS
VP15-00-1
Wave Soldering
WS60-00-1
Pin Partial Heating
--
Caution: Do not use two or more soldering methods in combination (except the pin partial heating method).
Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235C, number of times: 2, and an extended number of days) is also available. For details, consult NEC.
58
PD75512(A)
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PD755XX(A) SERIES PRODUCTS
Product Item ROM Configuration ROM (Bit) RAM (Bit) Mask Option 12160 x 8
PD75512(A)
Mask ROM
PD75516(A)
PD75P516
EPROM/One-time PROM
16256 x 8 512 x 4
16256 x 8
* Ports 4, 5, 12, 14 are provided with internal pull-up resistors. * Port 9 is provided with an internal pull-down resistor. Not provided Not offered 2.7 to 6.0 V Differ in high-level / low-level output current
Not provided Provided Offered 4.75 to 5.5 V
VPP, PROM, Pins for programming LED Direct Drive Electrical Specifications Supply Voltage Range Absolute Maximum Ratings DC Characteristics A/D Converter Characteristics Quality Grade Package
Differ in low-level output voltage Differ in ambient temperature range and absolute accuracy
Special 80-pin plastic QFP (14 x 20 mm)
Standard * 80-pin plastic QFP (14 x 20 mm) * 80-pin ceramic WQFN
59
PD75512(A)
APPENDIX B. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
PD75512(A):
Hardware IE-75000-R *1 IE-75001-R IE-75000-R-EM *2 EP-75516GF-R EV-9200G-80 PG-1500 PA-75P516GF Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler * 1: Maintenance product In-circuit emulator for 75X series Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75512(A), provided with 80-pin conversion socket EV-9200G-80. PROM programmer PROM programmer adapter solely used for PD75P516GF. It is connected to PG-1500. Host machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3 ) IBM PC/AT TM (PC DOS TM Ver.3.1)
2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
60
PD75512(A)
APPENDIX C. RELATED DOCUMENTS
5
61
PD75512(A)
[MEMO]
62
PD75512(A)
GENERAL NOTES ON CMOS DEVICES
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
63
PD75512(A)
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.
64

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